View AT27C4096-90PI_4344503.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

features ? fast read access time ? 55 ns low power cmos operation ? 100 a maximum standby ? 40 ma maximum active at 5 mhz jedec standard packages ? 40-lead pdip ? 44-lead plcc ? 40-lead vsop direct upgrade from 512-k bit, 1-mbit, and 2-mbit (at27c516, at27c1024, and at27c2048) eproms 5v 10% power supply high reliability cmos technology ? 2,000v esd protection ? 200 ma latchup immunity rapid programming algorithm ? 50 s/word (typical) cmos and ttl compatible inputs and outputs integrated product identification code industrial temperature range green (pb/halide-free) packaging option 1. description the at27c4096 is a low-power, high-performance 4,194,304-bit one-time program- mable read-only memory (otp eprom) orga nized 256k by 16 bits. it requires a single 5v power supply in normal read mode operation. any word can be accessed in less than 55 ns, eliminating the need for speed-reducing wait states. the x16 organi- zation makes this part ideal for high- performance 16- and 32-bit microprocessor systems. in read mode, the at27c4096 typically consumes 15 ma. standby mode supply cur- rent is typically less than 10 a . the at27c4096 is available in industry-standard jedec-approved one-time pro- grammable (otp) plastic pdip, plcc, and vsop packages. the device features two-line control (ce , oe ) to eliminate bus contention in high-speed systems. with high density 256k word storage capab ility, the at27c4096 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. atmel?s at27c4096 has additional features that ensure high quality and efficient pro- duction use. the rapid programming algorithm reduces the time required to program the part and guarantees reliable programming. programming time is typically only 50 s/word. the integrated product identification code electronically identifies the device and manufacturer. this feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. 4-megabit (256k x 16) otp eprom at27c4096 0311i?eprom?12/07
2 0311i?eprom?12/07 at27c4096 2.1 44-lead plcc top view 2.2 40-lead pdip top view 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 o12 o11 o10 o9 o8 gnd nc o7 o6 o5 o4 a13 a12 a11 a10 a9 gnd nc a8 a7 a6 a5 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 o3 o2 o1 o0 oe nc a0 a1 a2 a3 a4 o13 o14 o15 ce vpp nc vcc a17 a16 a15 a14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 vpp ce o15 o14 o13 o12 o11 o10 o9 o8 gnd o7 o6 o5 o4 o3 o2 o1 o0 oe vcc a17 a16 a15 a14 a13 a12 a11 a10 a9 gnd a8 a7 a6 a5 a4 a3 a2 a1 a0 2.3 40-lead vsop (t ype 1) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a9 a10 a11 a12 a13 a14 a15 a16 a17 vcc vpp ce o15 o14 o13 o12 o11 o10 o9 o8 gnd a8 a7 a6 a5 a4 a3 a2 a1 a0 oe o0 o1 o2 o3 o4 o5 o6 o7 gnd 2. pin configurations note: both gnd pins must be connected. pin name function a0 - a17 addresses o0 - o15 outputs ce chip enable oe output enable nc no connect
3 0311i?eprom?12/07 at27c4096 3. system considerations switching between active and standby conditions via the chip enable pin may produce tran- sient voltage excursions. unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. at a minimum, a 0.1 f high frequency, low inherent inductan ce, ceramic capacitor should be utilized for each device. this capacitor should be connected between the v cc and ground terminals of the device, as close to the device as possible. additionally, to stabi lize the supply voltage level on printed circuit boards with large eprom arrays, a 4.7 f bulk electrolytic capacitor should be utilized, again connected between the v cc and ground terminals. this capacitor should be positioned as close as possible to the point where the power supply is connected to the array. 4. block diagram note: 1. maximum voltage is -0.6v dc which may undershoot to -2 .0v for pulses of less than 20 ns. maximum output pin voltage is v cc + 0.75v dc which may overshoot to +7.0v for pulses of less than 20 ns. 5. absolute maximum ratings* temperature under bias............................... -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -65 c to +150 c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on a9 with respect to ground ......................................-2.0v to +14.0v (1) v pp supply voltage with respect to ground .......................................-2.0v to +14.0v (1)
4 0311i?eprom?12/07 at27c4096 notes: 1. x can be v il or v ih . 2. refer to the programming characteristics. 3. v h = 12.0 0.5v. 4. two identifier words may be selected. all ai inputs are held low (v il ), except a9, which is set to v h , and a0, which is toggled low (v il ) to select the manufacturer?s identification word and high (v ih ) to select the device code word. 5. standby v cc current (i sb ) is specified with v pp = v cc . v cc > v pp will cause a slight increase in i sb . notes: 1. v cc must be applied simultaneously or before v pp , and removed simultaneously or after v pp . 2. v pp may be connected directly to v cc , except during programming. the supp ly current would then be the sum of i cc and i pp . 6. operating modes mode/pin ce oe ai v pp outputs read v il v il ai x (1) d out output disable x v ih x x high z standby v ih xx x (5) high z rapid program (2) v il v ih ai v pp d in pgm verify v ih v il ai v pp d out pgm inhibit v ih v ih xv pp high z product identification (4) v il v il a9 = v h (3) a0 = v ih or v il a1 - a17 = v il v cc identification code 7. dc and ac operating cond itions for read operation at27c4096 -55 -90 industrial operating temperature (case) -40 c - 85 c-40 c - 85 c v cc power supply 5v 10% 5v 10% 8. dc and operating characteristics for read operation symbol parameter condition min max units i li input load current v in = 0v to v cc 1a i lo output leakage current v out = 0v to v cc 5a i pp1 (2) v pp (1) read/standby current v pp = v cc 10 a i sb v cc (1) standby current i sb1 (cmos) ce = v cc 0.3v 100 a i sb2 (ttl) ce = 2.0 to v cc + 0.5v 1ma i cc v cc active current f = 5 mhz, i out = 0 ma, ce = v il 40 ma v il input low voltage -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 a 2.4 v
5 0311i?eprom?12/07 at27c4096 note: 1. see the ac waveforms for read operation diagram. 10. ac waveforms for read operation (1) notes: 1. timing measurement references are 0.8v and 2.0v. input ac drive levels are 0.45v and 2.4v, unless otherwise specified. 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce . 3. oe may be delayed up to t acc - t oe after the address is valid without impact on t acc . 4. this parameter is only sampled and is not 100% tested. 5. output float is defined as t he point when data is no longer driven. 9. ac characteristics for read operation symbol parameter condition at27c4096 units -55 -90 min max min max t acc (1) address to output delay ce = oe = v il 55 90 ns t ce (1) ce to output delay oe = v il 55 90 ns t oe (1) oe to output delay ce = v il 20 35 ns t df (1) oe or ce high to output float, whichever occurred first 20 20 ns t oh (1) output hold from address, ce or oe , whichever occurred first 70ns
6 0311i?eprom?12/07 at27c4096 11. input test waveform s and measurement levels for -55 devices only: t r , t f < 5 ns (10% to 90%) for -90 devices: t r , t f < 20 ns (10% to 90%) 12. output test load note: cl = 100 pf including jig capacitance. note: 1. typical values for nominal supply voltage. th is parameter is only samp led and is not 100% tested. output pin 1.3v (1n914) 3.3k cl 13. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 410pfv in = 0v c out 812pfv out = 0v
7 0311i?eprom?12/07 at27c4096 14. programming waveforms (1) notes: 1. the input timing reference is 0.8v for v il and 2.0v for v ih . 2. t oe and t dfp are characteristics of the device but must be accommodated by the programmer. 3. when programming the at27c4096, a 0.1 f capacitor is required across v pp and ground to suppress spurious voltage transients.
8 0311i?eprom?12/07 at27c4096 notes: 1. v cc must be applied simultaneously or before v pp and removed simultaneously or after v pp . 2. this parameter is only sampled and is not 100% tested. output float is defined as the point where data is no longer driven ? see timing diagram. 3. program pulse width tolerance is 50 sec 5%. 15. dc programming characteristics t a = 25 5c, v cc = 6.5 0.25v, v pp = 13.0 0.25v symbol parameter test conditions limits units min max i li input load current v in = v il , v ih 10 a v il input low level -0.6 0.8 v v ih input high level 2.0 v cc + 0.7 v v ol output low voltage i ol = 2.1 ma 0.4 v v oh output high voltage i oh = -400 a 2.4 v i cc2 v cc supply current (program and verify) 50 ma i pp2 v pp supply current ce = v il 30 ma v id a9 product identification voltage 11.5 12.5 v 16. ac programming characteristics t a = 25 5c, v cc = 6.5 0.25v, v pp = 13.0 0.25v symbol parameter test conditions (1) limits units min max t as address setup time input rise and fall times : (10% to 90%) 20 ns input pulse levels: 0.45v to 2.4v input timing reference level: 0.8v to 2.0v output timing reference level: 0.8v to 2.0v 2s t oes oe setup time 2 s t ds data setup time 2 s t ah address hold time 0 s t dh data hold time 2 s t dfp oe high to output float delay (2) 0130ns t vps v pp setup time 2 s t vcs v cc setup time 2 s t pw ce program pulse width (3) 47.5 52.5 s t oe data valid from oe 150 ns t prt v pp pulse rise time during programming 50 ns 17. atmel?s at27c4096 intergra ted product identification code codes pins hex data a0 o15-o8 o7 o6 o5 o4 o3 o2 o1 o0 manufacturer 0 0 0 0 0 1 1 1 1 0 001e device type 1 0 11110100 00f4
9 0311i?eprom?12/07 at27c4096 18. rapid programming algorithm a 50 s ce pulse width is used to program. the address is set to the first location. v cc is raised to 6.5v and v pp is raised to 13.0v. each address is first programmed with one 50 s ce pulse without verification. then a verification/reprogramming loop is executed for each address. in the event a word fails to pass verification, up to 10 successive 50 s pulses are applied with a verification after each pulse. if the word fails to verify after 10 pulses have been applied, the part is considered failed. after the word verifies properly, the next address is selected until all have been checked. v pp is then lowered to 5.0v and v cc to 5.0v. all words are read again and compared with the original data to determine if the device passes or fails.
10 0311i?eprom?12/07 at27c4096 19. ordering information note: 1. the 40-lead vsop package is not recommended for new designs. 19.1 standard package t acc (ns) i cc (ma) ordering code package operation range active standby 55 40 0.1 at27c4096-55ji at27c4096-55pi at27c4096-55vi 44j 40p6 40v (1) industrial (-40 c to 85 c) 90 40 0.1 at27c4096-90ji AT27C4096-90PI at27c4096-90vi 44j 40p6 40v (1) industrial (-40 c to 85 c) note: not recommended for new designs. use green package option. 19.2 green package (pb/halide-free) t acc (ns) i cc (ma) ordering code package operation range active standby 55 40 0.1 at27c4096-55ju at27c4096-55pu 44j 40p6 industrial (-40 c to 85 c) 90 40 0.1 at27c4096-90ju at27c4096-90pu 44j 40p6 industrial (-40 c to 85 c) package type 44j 44-lead, plastic j-leaded chip carrier (plcc) 40p6 40-lead, 0.600" wide, plastic dual inline package (pdip) 40v 40-lead, plastic thin small outline package (vsop)
11 0311i?eprom?12/07 at27c4096 20. packaging information 20.1 44j ? plcc notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.986 ? 16.002 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev.
12 0311i?eprom?12/07 at27c4096 20.2 40p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 52.070 ? 52.578 note 2 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 2 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
13 0311i?eprom?12/07 at27c4096 20.3 40v ? vsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40v , 40-lead (10 x 14 mm package) plastic thin small outline package, type i (vsop) b 40v 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 seating plane 0o ~ 8o c l l1 gage plane common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation ca. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 13.80 14.00 14.20 d1 12.30 12.40 12.50 note 2 e 9.90 10.00 10.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
0311i?eprom?12/07 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support eprom@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or co mpleteness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. ? 2007 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others ar e registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

▲Up To Search▲

Price & Availability of AT27C4096-90PI

	To Download AT27C4096-90PI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .